Xilinx Design Summary

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	8	9,312	1%
Number of 4 input LUTs	12	9,312	1%
Logic Distribution
Number of occupied Slices	7	4,656	1%
Number of Slices containing only related logic	7	7	100%
Number of Slices containing unrelated logic	0	7	0%
Total Number of 4 input LUTs	12	9,312	1%
Number of bonded IOBs	11	232	4%
Number of GCLKs	1	24	4%
Total equivalent gate count for design	139
Additional JTAG gate count for IOBs	528

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met